`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/10 22:38:33
// Design Name: 
// Module Name: IF
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module IF(
    input wire clk,
    input wire rst,
    input wire pause,

    // jump or not
    input wire i_is_jump,
    // jump to
    input wire [31:0] i_new_inst_addr,

    // output inst addr
    output wire [31:0] o_inst_addr
    );
    
    reg [31:0] pc = 0;
    
    assign o_inst_addr = i_is_jump ? i_new_inst_addr
        : pc;
    
    always @(posedge clk) begin
        if (rst == 1) begin
            if (pause == 0) begin
                if (i_is_jump) begin
                    pc <= i_new_inst_addr + 4;
                end else begin
                    pc <= pc + 4;
                end
            end
        end else begin
            pc <= 0;
        end
    end
    
endmodule
